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https://hdl.handle.net/20.500.12104/95504| Title: | Retos Sobre el Modelado del Transistor de Compuerta Flotante de Múltiples Entradas en Circuitos Integrados - Challenges on Modeling of Floating Gate Transistor Multiple Entries Integrated Circuits |
| Keywords: | CMOS;Analógico;Circuitos;Integrados;Compuerta-flotante;muy bajo voltaje |
| Publisher: | Universidad de Guadalajara |
| Description: | En este artículo se presentan las consideraciones que hay que adoptar para el uso del transistor de compuerta flotante de múltiples entradas para el diseño de circuitos integrados analógicos. Para ello se presentan las principales características de este transistor así como sus principales ventajas con respecto al transistor MOSFET convencional que este dispositivo ofrece. También, se exponen los principales problemas que han frenado el uso de este dispositivo en el ámbito comercial debido a la falta de modelos precisos.Abstract: In this paper are presented the considerations that we have to adopt to use the floting gate transistor of multiple entries to to design analogic integrated circuits. To get in that, here are presented the main characteristics of this transistor and its main advantages respecting to conventional MOSFET transistor that this device offers. Also, main problems that have stopped the usage of this device in the commercial environment due the lack of exact models are expossedKeywords: CMOS, Analogic, Circuits, Integrated, floting-gate, Very low voltage |
| URI: | https://hdl.handle.net/20.500.12104/95504 |
| Other Identifiers: | http://recibe.cucei.udg.mx/index.php/ReCIBE/article/view/5 10.32870/recibe.v1i1.5 |
| Appears in Collections: | Revista ReCIBE |
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